Requirements: English
Company: Fortaegis Technologies
Region: Amsterdam , North Holland
FPGA/ASIC Engineer
Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for an experienced FPGA/ASIC Engineer with a strong background in RTL coding to join the hardware engineering team. In this role, you will design, implement and optimize FPGA and ASIC solutions. The ideal candidate will have hands-on experience with digital design - preferably using Verilog - and will collaborate closely with cross-disciplinary teams to develop high-performance systems. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our breakthrough product even better.
Responsibilities:
- RTL Development for FPGA and/or ASIC design
- Design and implement digital circuits using RTL coding in Verilog (or VHDL).
- Translate system-level requirements into efficient architectures.
- Develop, synthesize, and optimize designs for timing, power, and area efficiency.
- Use FPGA development tools like Xilinx Vivado for synthesis, place-and-route, and optimization.
- Ensure design compliance with timing, power, and area constraints through post-synthesis and post-route analysis.
- Apply RTL design best practices, such as modularity, code reuse, and proper pipelining techniques.
- Create and maintain detailed documentation for RTL designs, including specifications and user manuals.
- Provide regular project updates, reporting progress against key milestones and identifying risks early.
- Work closely with hardware engineers, software developers and system architects to define FPGA and ASIC requirements and integrate designs into the final product.
- Stay updated with the latest FPGA technologies, tools, and best practices, and evaluate new solutions for potential projects.
- Experience with UVM is nice to have.
Requirements:
- Bachelor''s degree in electrical engineering, Computer Engineering, or a related field. A master''s degree is a plus.
- 3+ years of experience in RTL coding.
- Experience with FPGA and ASIC development.
- Proficiency in Verilog for digital design.
- Experience in the design and development of FPGA-based systems for high-performance or real-time applications.
- Hands-on experience with FPGA platforms like Xilinx, Intel/Altera.
- Strong knowledge of RTL design, digital logic, and finite state machines.
- Familiarity with synthesis, place-and-route, and timing closure methodologies.
- Experience with SoC design is a big plus.
The successful candidate will have the unique opportunity to participate in shaping the design of our groundbreaking product, contributing to the development of ultra-secure and high-performance SoC designs. They will be part of a dynamic and innovative team, working in a collaborative and challenging environment at the forefront of semiconductor technology.