Would you like to work on building world-first, ultra-secure SoCs from the ground up?
Do you want to take ownership of the verification environment for bleeding-edge semiconductor designs?
Are you looking to be part of a dynamic and fast-scaling team shaping tomorrow''s chip architecture?
Our client is at a pivotal growth stage, transitioning from early prototyping to large-scale development and industrialization. The biggest challenge? Building a robust, scalable verification infrastructure capable of keeping pace with rapid design cycles and complex integration - all without legacy constraints holding you back.
I''m looking for someone who:
Has 5+ years of hands-on ASIC verification experience
Is an expert in UVM and SystemVerilog with a solid understanding of logic design
Has verified processor-based SoC systems, ideally with interfaces like PCIe, DDR, UCIe, or Ethernet
Is comfortable with scripting (Tcl, Python, Perl) and familiar with HW/SW co-simulation tools
Who is interested in:
Developing and maintaining complex UVM-based testbenches
Collaborating with design and architecture teams to ensure quality and alignment
Influencing verification strategy and infrastructure from day one
Solving real-time debug and integration challenges
Growing within a company that rewards initiative and innovation
For a company who:
Is building a ground-breaking, high-performance SoC with built-in security from scratch
Offers full autonomy and a chance to influence verification processes end-to-end
Provides a highly collaborative, agile, and ambitious engineering environment
Operates at the cutting edge of chip architecture, with a fast track to productization
We know we ask a lot but encourage you to apply even if you fit 80% of the role.
Apply now! Chat first? Call Febraneila Primadina Kusuma at +31 (0)20 305 0079 or e-mail me at febraneila.kusuma@darwinrecruitment.com to learn more about this exciting opportunity.
Darwin Recruitment is acting as an Employment Agency in relation to this vacancy.