Principal Design Engineer

vaud, switzerland , Vaud, Switzerland

Type: n/a

Category: Creative Industries

Requirements: English
Company: TN Switzerland
Region: vaud, switzerland , Vaud

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Client:

microTECH Global Ltd

Location:

Switzerland

Job Reference:

8ca064e51cdb

Job Views:

3

Posted:

02.04.2025

Expiry Date:

17.05.2025

Job Description:

Role: Principal Design Engineer
About the role:
You must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both technical and leadership skills, while working closely with multi-disciplinary groups to drive & design key aspects of ASIC/pwr mgmt.

Candidate will be lead designer, support verification, and be technical focus on one or more device and/or sections. Candidate will also support pre/post-silicon design validation and support Design/ATE/Application & Systems group.

Products working on:
switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.

Responsibilities:

1. Support & develop the chip/digital level architecture and functional blocks
2. Provide technical documentation with specifications, block diagrams, and requirements to stakeholders.
3. Collaborate & work with departments/stakeholders including for architectures, requirements, and tradeoffs, including Digital/Analog Design, Application/Test Engineering, & Reliability/Operations to resolve design, application, or test issues.
4. Develop system and chip level simulation verification techniques and methodology.
5. Digital Design (RTL design): ASIC or FPGA from concept to implementation
6. Digital Verification: Development test plans, test benches and automated test cases
7. Knowledge and/or responsibility in synthesis, timing closure, and formal verification.
8. Create scripting to support design and verification automation
9. Estimate and manage time/tasks completion to target schedule

Qualifications:

1. PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
2. 10+ years experience in design plus verification of ASIC or FPGA
3. Broad & Strong knowledge of ASIC development process and digital design techniques.
4. Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics.
5. Experience with programming, scripting and automation languages(C/C++, shell, Perl, TCL, Python, etc).
6. Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
7. Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
8. Good written/verbal communication skills and strong team work/collaboration.

Experience with the following is highly desired:

1. Knowledge of power management architectures/applications
2. I2C, I3C, SPI, USB, PMBUS, I2S, CANOpen, EtherCAT
3. GITLab or equiv version control
4. Embedded MCU(ARM) designs and/or firmware development
5. Previous experience in signal processing and sensors

If you are interested in this role please apply.

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